This invention relates to linking parallel processors in a parallel processor system, and more particularly to a parallel processor configuration and mounting ideally suitable for high speed parallel processing.
JP-B-63-124162 (hereinafter referred to as the first prior art example) is an example of a conventional parallel processor system configuration constituted by a plurality of parallel processors that each execute a parallel processing program (hereinafter referred to as the computing clusters) and a network that enables data to be transferred between computing clusters. In this parallel processor system, the computing clusters are arranged in a two-dimensional array consisting of 2.sup.m rows vertically and 2.sup.n columns horizontally (where m and n are positive integers), and each of the rows (X direction) and columns (Y direction) of the array is provided with a crossbar switch. Each of the computing clusters is connected to an X direction crossbar switch and a Y direction crossbar switch. To provide the connections with the X direction crossbar switch and the Y direction crossbar switch, each of the computing clusters has two input/output ports (hereinafter referred to simply as ports). In the following, this network of crossbar switches provided in each dimension is referred to as a partial crossbar network.
In NCUBE's (hereinafter referred to as the second prior art example), on the other hand, input/output processors (auxiliary processors) are linked together in a hypercube network configuration (see for example, pages 236 and 238 of "Everything About 32-bit Microprocessors: Corporate Strategies, Technology, Market Trends," published by Nikkei McGraw-Hill, December 1986). To realize this, each node processor has a number of ports equal to the number of hypercube dimensions plus one. The number of ports equal to the number of hypercube dimensions are connected to each of the other node processors, and the remaining port is connected to the input/output processor. That is, each node processor uses a dedicated port to provide a connection with an auxiliary processor.
Mounting of parallel processors in a partial crossbar network has been described in the prior art in, for example, C. Chin, "A Massively Parallel Processing System Based on a Hyper-Crossbar Network", the Second Symposium on the Frontiers of Massively Parallel Computation, Oct. 10-12 1988, pp. 463-466, and in Nobour Tanake et al, "Hardware of Prodigy Parallel AI Machine", the research report of the Institute of Electronics, Information and Communications Engineers, CPSY 89-45 to 58, March 1989, pp. 39-44, in Japanese (hereinafter referred to as the third and fourth prior art examples, respectively).
In the third prior art example, the parallel processor system is configured as a two-dimensional partial crossbar network. One crossbar switch, referred to as a local crossbar network, and the processor group connected thereto are mounted on one wafer. The other crossbar switch, referred to as a global crossbar network, is mounted on its own separate LSI. The parallel processor system is configured by combining a plurality of these wafers and LSIs.
In the fourth prior art example, the parallel processor system is configured as a three-dimensional partial crossbar network. A group of X direction and Y direction crossbar switches corresponding to one plane and the processor group connected thereto are mounted on one frame. A group of Z direction crossbar switches is mounted on its own frame. The parallel processor system is configured by combining a plurality of these frames.
Of general interest are: Dharma P. Agrawal, et al, "Evaluating the Performance of Multicomputer Configurations", IEEE Computers, Vol. 19, No. 5, May 1986, pages 23-37; and Tse-yun Feng, "A Survey of Interconnection Networks", IEEE Computers, Vol. 14, No. 12, December 1981, pages 12-27.